SN65LVDT388ADBT - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN65LVDT388ADBT
Manufacturer

TI
ChipWorker Part#

CW21356192
Category

Interface IC, Interface Controller
Package

TSSOP-38
Description

TEXAS INSTRUMENTS SN65LVDT388ADBT Differential Line Receiver IC, 630Mbps Data Rate, 8 Receivers, 15kV ESD, 3V to 3.6V, TSSOP-38
Documentation

Datasheet

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SN65LVDT388ADBT Specifications

Attribute	Attribute Value

Part Number	SN65LVDT388ADBT
Manufacturer	TI
ChipWorker Part#	CW21356192
Category	Interface IC, Interface Controller
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	38 Pin
Case/Package	TSSOP-38
Supply Voltage (DC)	3.00V (min)
Supply Current	40 mA
Number of Positions	38 Position
Power Dissipation	1071 W
Data Rate	630 Mbps
Input Current (Min)	40 μA
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Power Dissipation (Max)	1071 mW
Supply Voltage	3V ~ 3.6V
Supply Voltage (Max)	3.6 V
Supply Voltage (Min)	3 V
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Size-Length	9.7 mm
Size-Width	4.4 mm
Size-Height	1.15 mm
Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The SN65LVDT388ADBT is an octal differential Line Receiver implements the electrical characteristics of low-voltage differential signalling (LVDS). This signalling technique lowers the output voltage levels of 5V differential standard levels (such as EIA/TIA-422B) to reduce the power, increase the switching speeds and allow operation with a 3V supply rail. Any of the differential receivers provides a valid logical output state with a ±100mV differential input voltage within the input common-mode voltage range. The input common-mode voltage range allows 1V of ground potential difference between two LVDS nodes. Additionally, the high-speed switching of LVDS signals almost always requires the use of a line impedance matching resistor at the receiving end of the cable or transmission media. The LVDT products eliminate this external resistor by integrating it with the receiver.
Open-circuit failsafe
Flow-through pin-out
Integrated 110R line termination resistors on LVDT products
Bus-terminal ESD exceeds 15kV
2.6ns Typical propagation delay time
100ps Typical output skew
<1ns Part-to-part skew
630Mbps Signalling rate
Green product and no Sb/Br

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