ADCLK948BCPZ ,Clock Buffer, Driver, PLL IC - ADI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Popularity Score

179 points

Part No

ADCLK948BCPZ
Manufacturer

ADI
ChipWorker Part#

CW494887
Category

Clock Buffer, Driver, PLL IC
Package

LFCSP-32
Description

Clock Multiplexer 8Out 2IN 1:8 32Pin LFCSP EP Tray
Documentation

Datasheet
Ships from

Moscow
Наличие

In Stock
Estimated Price

$ 8.79

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ADCLK948BCPZ Specifications

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Attribute	Attribute Value

Part Number	ADCLK948BCPZ
Manufacturer	ADI
ChipWorker Part#	CW494887
Category	Clock Buffer, Driver, PLL IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	32 Pin
Case/Package	LFCSP-32
Frequency	4.8 GHz
Supply Voltage (DC)	2.97V (min)
Number of Outputs	8 Output
Supply Current	288 mA
Number of Circuits	1 Circuit
Number of Positions	32 Position
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	2.97V ~ 3.63V
Supply Voltage (Max)	3.63 V
Supply Voltage (Min)	2.97 V
	expand all
Size-Length	5 mm
Size-Width	5 mm
Size-Height	0.83 mm
Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tray
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2013/06/20
ECCN Code	EAR99

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Product Description

The ADCLK948BCPZ is an ultrafast SiGe clock Fanout Buffer with two selectable inputs and 8 LVPECL outputs. It is designed for high speed applications requiring low jitter. The device has two selectable differential inputs via the IN SEL control pin. Both inputs are equipped with center tapped, differential, 100R on-chip termination resistors. The inputs accept DC-coupled LVPECL, CML, 3.3V CMOS (single-ended) and AC-coupled 1.8V CMOS, LVDS and LVPECL inputs. A VREFx pin is available for biasing AC-coupled inputs. The ADCLK948 features eight full-swing emitter coupled logic (ECL) output drivers. For LVPECL (positive ECL) operation, bias VCC to the positive supply and VEE to ground. For ECL operation, bias VCC to ground and VEE to the negative supply. The output stages are designed to directly drive 800mV each side into 50R terminated to VCC.
On-chip input terminations
75fs RMS Broadband random jitter

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