CD74HCT165E - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

CD74HCT165E
Manufacturer

TI
ChipWorker Part#

CW11529600
Category

Shift Register IC
Package

DIP-16
Description

TEXAS INSTRUMENTS CD74HCT165E Shift Register, HCT Family, 74HCT165, Parallel to Serial, 1Element, 8Bit, DIP, 16Pins
Documentation

Datasheet

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CD74HCT165E Specifications

Attribute	Attribute Value

Part Number	CD74HCT165E
Manufacturer	TI
ChipWorker Part#	CW11529600
Category	Shift Register IC
Documentation	Datasheet
Mounting Style	Through Hole
Number of Pins	16 Pin
Case/Package	DIP-16
Frequency	18 MHz
Supply Voltage (DC)	5.00 V, 5.50 V (max)
Number of Outputs	1 Output
Number of Circuits	1 Circuit
Number of Positions	16 Position
Number of Bits	8 Bit
Number of Inputs	9 Input
Operating Temperature (Max)	125 ℃
Operating Temperature (Min)	-55 ℃
Supply Voltage	4.5V ~ 5.5V
Supply Voltage (Max)	5.5 V
Supply Voltage (Min)	4.5 V
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Size-Length	19.3 mm
Size-Width	6.35 mm
Size-Height	4.57 mm
Weight	0.015227096868 kg
Operating Temperature	-55℃ ~ 125℃
Product Lifecycle Status	Active
Packaging	Each
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The CD74HCT165E is a 8-bit CMOS parallel-in/serial-out Shift Register with complementary serial outputs (Q7 and Q7\\) available from the last stage. When the parallel load (PL\\) input is low, parallel data from the D0 to D7 inputs are loaded into the register asynchronously. When the PL\ is high, data enters the register serially at the DS input and shifts one place to the right (Q0 → Q1 → Q2, etc.) with each positive-going clock transition. This feature allows parallel-to-serial converter expansion by typing the Q7output to the DS input of the succeeding device. For predictable operation the low-to-high transition of CE\ should only take place while CP is high. Also, CP and CE\ should be low before the low-to-high transition of PL to prevent shifting the data when PL\ goes high.
Buffered inputs
Asynchronous parallel load
Complementary outputs
Balanced propagation delay and transition times
Significant power reduction compared to LSTTL logic ICs
High noise immunity
Direct LSTTL input logic compatibility
CMOS Input compatibility
10 LSTTL Loads standard outputs
15 LSTTL Loads bus driver outputs

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