SN65LVDS105PW - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN65LVDS105PW
Manufacturer

TI
ChipWorker Part#

CW33172410
Category

LVDS, M-LVDS, ECL, CML IC
Package

TSSOP-16
Description

LVDS Receiver 400Mbps 0.454V 16Pin TSSOP Tube
Documentation

Datasheet

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SN65LVDS105PW Specifications

Attribute	Attribute Value

Part Number	SN65LVDS105PW
Manufacturer	TI
ChipWorker Part#	CW33172410
Category	LVDS, M-LVDS, ECL, CML IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	16 Pin
Case/Package	TSSOP-16
Supply Voltage (DC)	3.30 V
Number of Outputs	4 Output
Supply Current	23 mA
Number of Positions	16 Position
Power Dissipation	774 mW
Input Capacitance	3 pF
Input Current (Min)	35 μA
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Power Dissipation (Max)	774 mW
Supply Voltage	3V ~ 3.6V
Supply Voltage (Max)	3.6 V
Supply Voltage (Min)	3 V
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Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The SN65LVDS105PW is a LVDS Clock Fan-out Buffer for network routers. The differential line receiver and a LVTTL input (respectively) connected to four differential line drivers that implement the electrical characteristics of low-voltage differential signaling (LVDS). LVDS, as specified in EIA/TIA-644 is a data signaling technique that offers low-power, low-noise coupling and switching speeds to transmit data at relatively long distances. The intended application of this device and signaling technique is for point-to-point baseband data transmission over controlled impedance media of approximately 100R. The transmission media may be printed-circuit board traces, backplanes or cables. Having the drivers integrated into the same substrate, along with the low pulse skew of balanced signalling, allows extremely precise timing alignment of the signals repeated from the input. This is particularly advantageous in distribution or expansion of signals such as clock/serial data stream.
Electrically compatible with LVDS, PECL, LVPECL, LVTTL, SSTL or HSTL outputs with external networks
Low-voltage differential signaling with typical output voltage of 350mV and a 100R load
LVTTL levels are 5V tolerant
Driver outputs are high-impedance when disabled or with VCC <1.5V
400MHz Clock frequency
2.2ns Typical propagation delay time

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