SN74HC74D ,Flip Flop IC - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

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133 points

Part No

SN74HC74D
Manufacturer

TI
ChipWorker Part#

CW1313700
Category

Flip Flop IC
Package

SOIC-14
Description

Flip Flop D-Type Pos-Edge 2Element 14Pin SOIC Tube
Documentation

Datasheet
Ships from

Moscow
Наличие

In Stock
Estimated Price

$ 0.1

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SN74HC74D Specifications

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Attribute	Attribute Value

Part Number	SN74HC74D
Manufacturer	TI
ChipWorker Part#	CW1313700
Category	Flip Flop IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	14 Pin
Case/Package	SOIC-14
Frequency	29 MHz
Supply Voltage (DC)	2.00V ~ 6.00V
Number of Outputs	1 Output
Output Voltage	5.00 V
Output Current	5.2 mA
Number of Circuits	2 Circuit
Number of Channels	2 Channel
Number of Positions	14 Position
Clock Speed	60 MHz
Number of Bits	2 Bit
Propagation Delay Max (tpd)	37.0 ns
Polarity	Non-Inverting, Inverting
Voltage Nodes	6.00 V, 5.00 V, 2.00 V
Input Capacitance	3 pF
Output Current Drive	-1.00 mA
Number of Inputs	1 Input
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	2V ~ 6V
Supply Voltage (Max)	6 V
Supply Voltage (Min)	2 V
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Size-Length	8.65 mm
Size-Width	3.91 mm
Size-Height	1.58 mm
Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2014/12/17
ECCN Code	EAR99

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Product Description

The SN74HC74D is a dual positive-edge-triggered D-type Flip-flop with clear and preset. This device contains two independent D-type positive-edge-triggered flip-flops. A low level at the preset (PRE\\) or clear (CLR\\) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the data (D) input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of CLK. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
Outputs can drive up to 10 LSTTL loads
15ns Typical tpd
Very low input current of 1µA
±4mA Output drive at 5V
40µA Maximum low power consumption

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