SN74LVC240APWR - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN74LVC240APWR
Manufacturer

TI
ChipWorker Part#

CW15178523
Category

Logic Control, Logic Gate IC
Package

TSSOP-20
Description

Buffer/Line Driver 8CH Inverting 3-ST CMOS 20Pin TSSOP T/R
Documentation

Datasheet

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SN74LVC240APWR Specifications

Attribute	Attribute Value

Part Number	SN74LVC240APWR
Manufacturer	TI
ChipWorker Part#	CW15178523
Category	Logic Control, Logic Gate IC
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	20 Pin
Case/Package	TSSOP-20
Supply Voltage (DC)	2.00V ~ 3.60V
Number of Outputs	8 Output
Number of Circuits	2 Circuit
Number of Channels	8 Channel
Number of Positions	20 Position
Number of Bits	8 Bit
Propagation Delay Max (tpd)	7.50 ns
Voltage Nodes	3.30 V, 2.70 V, 2.50 V, 1.80 V
Output Current Drive	-1.00 mA
Number of Inputs	8 Input
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	1.65V ~ 3.6V
Supply Voltage (Max)	3.6 V
Supply Voltage (Min)	1.65 V
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Size-Length	6.5 mm
Size-Width	4.4 mm
Size-Height	1.05 mm
Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tape & Reel (TR)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

Product Description

The SN74LVC240APWR is an octal Buffer/Driver designed for 1.65 to 3.6V VCC operation. It is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers and bus-oriented receivers and transmitters. This device is organized as two 4-bit buffers/drivers with separate output-enable (OE) inputs. When OE is low, the device passes data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state. Inputs can be driven from either 3.3/5V devices. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor and the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using IOFF. The IOFF circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
IOFF Supports live insertion, partial-power-down mode and back-drive protection
Allows down voltage translation
Supports mixed-mode signal operation on all ports
Latch-up performance exceeds 250mA per JESD 17
6.5ns at 3.3V Propagation delay (tpd)
<0.8V at VCC = 3.3V, TA = 25°C VOLP (output ground bounce)
>2V at VCC = 3.3V, TA = 25°C VOHV (output VOH undershoot)
Green product and no Sb/Br

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