SN65LVDT386DGG - TI

The pictures are for reference only, and the specific specifications can be found in the product manual.

Part No

SN65LVDT386DGG
Manufacturer

TI
ChipWorker Part#

CW11869933
Category

Interface IC, Interface Controller
Package

TSSOP-64
Description

LVDS PHY (<800Mbps) 16Channel Receiver LVDS Receiver 630Mbps 64Pin TSSOP Tube
Documentation

Datasheet

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SN65LVDT386DGG Specifications

Attribute	Attribute Value

Part Number	SN65LVDT386DGG
Manufacturer	TI
ChipWorker Part#	CW11869933
Category	Interface IC, Interface Controller
Documentation	Datasheet
Mounting Style	Surface Mount
Number of Pins	64 Pin
Case/Package	TSSOP-64
Supply Voltage (DC)	3.00V (min)
Supply Current	70 mA
Input Current	70.0 mA
Power Dissipation	2094 W
Data Rate	630 Mbps
Input Current (Min)	40 μA
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Power Dissipation (Max)	2094 mW
Supply Voltage	3V ~ 3.6V
Supply Voltage (Max)	3.6 V
Supply Voltage (Min)	3 V
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Size-Length	17 mm
Size-Width	6.1 mm
Size-Height	1.15 mm
Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99
HK STC License	NLR

Product Description

DESCRIPTION
This family of four-, eight-, or sixteen-, differential line receivers (with optional integrated termination) im
plements the electrical characteristics of low-voltage differential signaling (LVDS). This signaling technique
lowers the output voltage levels of 5-V differential standard levels (such as EIA/TIA-422B) to reduce the
power, increase the switching speeds, and allow operation with a 3-V supply rail.
FEATURES
• Four- ("390), Eight- ("388A), or Sixteen- ("386) Line Receivers Meet or Exceed the Requirements of ANSI TIA/EIA-644 Standard
• Integrated 110-Ω Line Termination Resistors on LVDT Products
• Designed for Signaling Rates(1) Up To 630 Mbps
• SN65 Version"s Bus-Terminal ESD Exceeds 15 kV
• Operates From a Single 3.3-V Supply
• Typical Propagation Delay Time of 2.6 ns
• Output Skew 100 ps (Typ) Part-To-Part Skew Is Less Than 1 ns
• LVTTL Levels Are 5-V Tolerant
• Open-Circuit Fail Safe
• Flow-Through Pinout
• Packaged in Thin Shrink Small-Outline Package With 20-mil Terminal Pitch

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